Under the high performance VGA standard, 24 bits (8 bits each for the red, green and blue color components) are used to specify a color. Because the number of pixels in a full screen is enormous, in many high-resolution graphics applications, neither providing a 24-bit wide data bus between the central processing unit (CPU) and the graphics display unit, nor providing a narrower but higher bandwidth bus, is economical. Instead, because the number of colors actually used at any given time is relatively small, as compared to the number of possible colors, a color palette containing a fixed but small number of color values is often used to reduce the bandwidth requirement. One popular color palette contains a 24-bit wide random access memory (RAM) storing 256 color values. To specify any one of the 256 color values, rather than the 24-bit color value, the CPU provides the address of a 24-bit word in the RAM; in this instance, the 256 addresses in the palette can be specified by eight bits. The 256 color values in the RAM is initialized at the beginning of the graphics operation, and can be dynamically updated by substituting new color values thereafter. As a result, since each color value is specified by its 8-bit address in the palette, the bandwidth requirement for such a system is much reduced from that required to specify the color value directly. Such system also reduces the size of the video frame buffer by two-thirds, since the 8-bit palette RAM addresses--rather than 24-bit color values --are stored in the video frame buffer.
A schematic representation of a color palette circuit 100 in the prior art is shown in FIG. 1. As shown in FIG. 1, the color palette circuit 100 consists of a 8-bit data port 107 sending and receiving both addresses and data during the reading or writing of color values in and out of the RAM 105. Because data port 107 is 8-bit wide, reading and writing a 24-bit color value requires multiple clock periods. Therefore, address register 101, and three 8-bit color registers 102a, 102b and 102c are provided internally for temporary storage during reading and writing of the RAM 105. During graphics operations, however, the addresses are received at every clock period over address lines P0-P7 at the 8-bit pixel address port 108, and a color value is provided in analog form at the output lines 110 every clock period.
In color palette circuit 100, RAM 105 can be configured as a 256.times.24-bit color palette 105, for storing 256 24-bit color values, or as a 256.times.18-bit color palette 105a, for storing 256 18-bit color values, with an additional 15.times.18-bit overlay palette 105b to implement additional functions known in the art, such as overlay cursors, or grids. In the latter mode, the address received at address port 108, which is stored in pixel register 103, is processed with the content of the pixel mask register 104 to provide an address for a color value in either the main color palette 105a, or the overlay palette 105b. Multiplexer 112 provides on address lines 113 either the pixel address on the address lines 114 and 115 or the address provided by address register 101 on lines 116, depending on whether output of a color value at the analog output lines 110, or an access such as loading a new color value, by the microprocessor is desired. Decoders (not shown) of RAM 105 decodes the address on lines 113 and provides read or write access to the RAM location specified on lines 113. For read operation, the output data of RAM 105 are tapped from lines 117. The write data lines into RAM 105 are not shown.
A color value read from RAM 105 is divided into its three color components before providing each to one of three digital-to-analog converters (DACs) 106a, 106b and 106c. Together, DACs 106a, 106b and 106c provide the analog signals suitable for driving an RGB type monitor. One color value is provided every clock cycle on the analog lines 110. Operation control for the color palette 100 is provided by control unit 109. Because color palette circuits, such as color palette circuit 100, comprise both RAM and DACs, they are also known as random access memory with digital-to-analog converters (RAMDACs).
In implementing the color palette circuit 100, a portion of the circuit is typically laid out in the manner shown in FIG. 2. RAM 105, sense amplifiers 111, DACs 106a, 106b and 106c, the color value register (CVR) 102, which is the combination of the individual color value registers 102a, 102b and 102c discussed above, and the analog lines 110 are shown. As can be seen from FIG. 2, because of the need to minimize the routing distance between the sense amplifiers 111 and the DACs 106a, 106b and 106c, the DAC structures are laid out very close to the sense amplifiers 111. Hence, the output values of the sense amplifiers 111 to the CVR 102 must also be tapped in the vicinity of the DACs structure, resulting in the need to route a 24-bit bus over a relatively long distance (area 120). Routing of such a wide bus is expensive in silicon area.
Furthermore, because the same sense amplifiers 111 are used to provide color values to both CVR 102 and the DACs 106a, 106b and 106c, the output data from the sense amplifiers 111 are often designed to multiplex between CVR 102 and DACs 106a, 106b and 106c, so that the color value read or written using an address supplied over port 107 is not provided to DACs 106a, 106b and 106c in the "video path" (i.e. the path from pixel address port 103 to analog color value output port 110). As a result, the color value provided by the RAM 105 to DACs 106a, 106b and 106c in the video path are also not available to CVR 102. As a result, it is not possible to probe from port 107 the digital color value supplied to DACs 106a, 106b, and 106c. Such probing capability is important for testing purposes. Hence, for a color value accessed by specifying a pixel address on port 108, only the analog output signals on lines 110 can be examined during test.
A 1-bit sense amplifier circuit 300, which is suitable for use with each bit of the 24-bit RAM 105 in the RAMDAC circuit 100, is shown in FIG. 3. As shown in FIG. 3, an enable signal EN enables the circuit 300 by turning on transistor 301, thereby providing a current path to the ground supply voltage through either transistors 302 and 305, or transistors 303 and 306. The value of the bit is specified by the input voltages on line COL, and its complementary signal NCOL. To provide performance, transistors 304 and 307 are used to drive the circuit 300 to the resolved state rapidly. In circuit 300, the "trip-point" of inverter 311 is set to be 2.5 volts, and the voltages on the lines COL and NCOL are constrained by transistors 308, 309 and 310 to be between 2.0 and 3.0 volts, so that state resolution is achieved by a relative small voltage swing of 1.0 volt. The output of the sense amplifier circuit 300 is provided by inverter 312, at the terminal OUT. Fourteen transistors in total are required for each bit of RAM 105's output data.
Another alternative in the prior art is to provide the RAM as a dual-port memory, such as discussed in the U.S. Pat. No. 4,905,189, entitled "System for Reading and Writing information," by M. Brunolli, filed Dec. 18, 1985 and issued Feb. 27, 1990. Dual-port memory requires almost double the amount of decoding necessary for a single-port memory. Such organization is too expensive in terms of silicon area, especially in view that access by the CPU is relatively infrequent in most applications. In addition, even a dual-port memory does not allow probing the color value output to the DAC structure 106 by the CPU at the same time it is provided to DAC 106.